1. Field of the Invention
The present invention relates generally to semiconductor processing and, more particularly, to a recessed structure and a method of forming the same.
2. Description of the Related Art
Microprocessor-controlled integrated circuits are used in a wide variety of applications. Such applications include personal computers, vehicle control systems, telephone networks, and a host of consumer products. As is well known, microprocessors are essentially generic devices that perform specific functions under the control of a software program. This software program is typically stored in a memory device coupled to the microprocessor. Not only does the microprocessor access the memory device to retrieve the program instructions, it also typically stores and retrieves data created during execution of the program in the memory device.
There are a wide variety of different memory devices available for use in microprocessor-based systems. The type of memory device chosen for a specific function within a microprocessor-based system depends largely upon what features of the memory are best suited to perform the particularly function. Most microprocessor-based systems include a dynamic random access memory (DRAM). DRAMs are volatile memories that must be continually powered in order to retain the contents. However, DRAMs are quite advantageous in that they tend to provide greater storage capability and programming cycles than non-volatile memories, such as read only memories.
A typical DRAM includes a memory array in which memory cells are arranged in rows and columns. Conductive lines, called word lines, connect the memory cells in a given row together, while perpendicular conductive lines, called digit lines, connect memory cells in a given column together. Each DRAM memory cell typically includes an access device, such as a transistor, and a storage device, such as a capacitor. Information is stored in each DRAM memory cell as the presence or absence of a charge on the storage capacitor. In response to the appropriate voltages on a selected word line and digit line, the access transistor couples the storage capacitor to the digit line so that a sense amplifier can determine whether the storage capacitor contains a charge, commonly called a logical one, or no charge, commonly called a logical zero.
To fabricate as many memory cells as possible on a single chip, the size of each memory cell should be minimized. However, the minimization of the size of a storage capacitor in a DRAM memory cell is typically limited by the amount of charge that the storage capacitor is able to retain. In fact, one of the primary concerns in DRAM fabrication is the desire to pack memory cells densely while maintaining the required capacitance levels of the storage capacitors. Simply put, it is essential that the plates of the storage capacitors be large enough to retain a charge adequate to allow the sense amplifiers to determine whether the storage capacitor is storing a logical one or a logical zero.
For years after the initial development of the basic DRAM memory cell, the storage capacitors were formed as two dimensional, or planar, capacitors. In other words, the storage capacitors were formed by two flat layers of conductive material, such as polysilicon or metal, separated by a flat dielectric layer. As the density of the memory cells increased and the size of the memory cells decreased, the size of the planar plates of the storage capacitors was clearly a limiting factor hindering further size reductions.
To reduce the size of DRAM memory cells further, and to provide storage capacitors with adequate capacitance, three dimensional capacitors were developed. One common three dimensional capacitor is referred to as a container capacitor. A container capacitor is fabricated by forming a container in a dielectric or insulative substrate. A conductive material, such as polysilicon, is deposited onto the substrate so that it lines the surface of the container. Similarly, a dielectric layer is deposited over the substrate so that it lines the polysilicon layer within the container. Finally, a second layer of conductive material, such as polysilicon, is deposited over the substrate so that it lines the dielectric layer within the container. Clearly, a container capacitor""s plates have a substantially greater area than a planar capacitor that occupies the same amount of die area.
Although container capacitors improved upon planar capacitors, they are not without their problems. During the fabrication of the first polysilicon layer of a container capacitor, it is not uncommon that residual polysilicon may remain on the substrate around the edge of the container. These polysilicon residues, sometimes called floaters, are conductive and, thus, can cause short circuits, typically between adjacent container capacitors in the memory array.
The present invention is directed to one or more of the problems set forth above.
In accordance with one aspect of the present invention, there is provided a microelectronic structure. The structure includes a container formed in a substrate which has an upper surface. A layer of conductive material is disposed in the container. The layer of conductive material has edges recessed below the upper surface of the substrate.
In accordance with another aspect of the present invention, there is provided a microelectronic structure. The structure includes a container formed in a dielectric material. The dielectric material has an upper surface, and the container has walls and a bottom surface. Conductive material is disposed on the walls and the bottom surface of the container. The conductive material on the walls is recessed below the upper surface of the dielectric material.
In accordance with still another aspect of the present invention, there is provided a capacitor in a semiconductor circuit. The capacitor includes a container formed in a substrate that has an upper surface. A first layer of conductive material is disposed in the container. The first layer of conductive material has edges recessed below the upper surface of the substrate. A layer of dielectric material is disposed over the first layer of conductive material. A second layer of conductive material is disposed on the layer of dielectric material.
In accordance with yet another aspect of the present invention, there is provided a memory cell for a semiconductor memory. The memory cell includes an access device and a capacitor coupled to the access device. The capacitor includes a container formed in a substrate that has an upper surface. A first layer of conductive material is disposed in the container. The first layer of conductive material has edges recessed below the upper surface of the substrate. A layer of dielectric material is disposed over the first layer of conductive material. A second layer of conductive material is disposed on the layer of dielectric material.
In accordance with a another aspect of the present invention, there is provided a method of forming a recessed microelectronic structure. The method includes the steps of: (a) forming a container in a dielectric material, the substrate having an upper surface; (b) disposing a layer of conductive material within the container and over the upper surface of the dielectric material; (c) disposing a layer of dissimilar material over the layer of conductive material; (d) removing the layer of dissimilar material and the layer of conductive material from at least a portion of the upper surface of the dielectric material; and (e) recessing the layer of conductive material remaining in the container below the upper surface of the container.
In accordance with an even further aspect of the present invention, there is provided a method of forming a recessed microelectronic structure. The method includes the steps of: (a) forming a container in a substrate, the substrate having an upper surface; (b) disposing a layer of conductive material within the container and over the upper surface of the substrate; (c) disposing a layer of photoresist over the layer of conductive material; (d) removing the layer of photoresist and the layer of conductive material from at least a portion of the upper surface of the substrate to expose a portion of the upper surface of the substrate adjacent the container; (e) recessing the layer of conductive material remaining in the container below the upper surface of the container; and (f) removing the layer of photoresist remaining in the container.
In accordance with a still further aspect of the present invention, there is provided a method of forming a recessed microelectronic structure. The method includes the steps of: (a) forming a container in a substrate, the substrate having an upper surface; (b) disposing a layer of conductive material within the container and over the upper surface of the substrate; (c) disposing a layer of photoresist over the layer of conductive material; (d) etching through a first portion of the layer of photoresist and a first portion of the layer of conductive material to expose a portion of the upper surface of the substrate adjacent the container; (e) etching through a second portion of the layer of photoresist remaining in the container; and (f) etching through a second portion of the layer of conductive material to remove the layer of conductive material from the upper surface of the substrate and to recess the layer of conductive material remaining in the container below the upper surface of the container.
In accordance with a yet further aspect of the present invention, there is provided a method of forming a capacitor in a microelectronic circuit. The method includes the steps of: (a) forming a container in a substrate, the substrate having an upper surface; (b) disposing a first layer of polysilicon within the container and over the upper surface of the substrate; (c) disposing a layer of photoresist over the first layer of polysilicon; (d) etching through a first portion of the layer of photoresist and a first portion of the first layer of polysilicon to expose a portion of the upper surface of the substrate adjacent the container; (e) etching through a second portion of the layer of photoresist remaining in the container; (f) etching through a second portion of the first layer of polysilicon to remove the first layer of polysilicon from the upper surface of the substrate and to recess the first layer of polysilicon remaining in the container below the upper surface of the container; (g) removing the layer of photoresist remaining in the container; (h) disposing a layer of dielectric material over the recessed first layer of polysilicon and over the upper surface of the substrate; (i) disposing a second layer of polysilicon over the layer of dielectric material; and (j) removing the layer of dielectric material and the second layer of polysilicon from the upper surface of the substrate.